The DES3 core implements the Triple Data Encryption Standard (DES3) documented in the U.S. Government publication FIPS 46-3.

The DES3 core is a block cipher, working on 64 bits of data at a time. It is built upon the Data Encryption Standard (DES) core. Key length is 64 bits of which only 56 bits are used. The DES3 core uses three independent keys. Encoding and decoding operations are performed in 48 clocks per block, in Electronic Codebook (ECB) mode.

The DES3 core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs.  The DES3 IP Core is delivered as Verilog RTL Source code.

The DES3 Low Gate version is implemented to minimize gate count or FPGA resources.  The design does not use any memories such as SRAM. 

The DES3 Pipelined version is implemented to maximize performance by pipelining the DES algorithm through three DES-PL instantiations.  After an initial latency of 48 cycles, it can output encryption/decryption at every cycle. The design does not use any memories such as SRAM.