公司：SLS

产品简介：The USB1.1 Device IP core is a universal serial bus (USB) function controller that provides a USB full-speed function interface and meets USB1.1 specification. This IP core is available with 3 standard endpoints (CTRL, BULK IN, and Bulk OUT ) configuration with maximum payload size. Each endpoint requires a FIFO to be associated with it. The FIFO size for the Endpoint 0 is fixed at 64 bytes and for Bulk IN and OUT is fixed at 128bytes (64x2 bytes). It is provided as Altera SOPC Builder ready component and integrates easily into any SOPC Builder generated system.

特色：Features
Verilog Implementation on RTL level
Supports full-speed (12 Mbps) transfer
USB enumeration support in harware
All interfaces are architected using a FIFO based model
Physical Layer Interface (UTMI compliant)
Avalon Interconnection complian
Extraction clock and data signals in internal digital phaseƒlocked loop (DPLL)
Cyclic redundancy code (CRC) checking/generation
Data toggle synchronization mechanism
Optimized for use with Altera Nios embedded processor

7. USB 1.1 Device Controller.rar