Features
Ø Reduced system complexity — No external glue logic required for typical
systems if chip selects are used.
Ø Three programmable asynchronous active-low chip selects can be independently
programmed with various features.
Ø Control for external boot device — CS0 can be selected as an external 16bit boot
device when in master mode.
Ø Fixed base addresses with 64-Mbyte block sizes
Ø Support for 8-bit 16-bit and 32-bit devices — The port size can be programmed
to be 8, 16 or 32 bits.
Ø Programmable write protection — Each chip select address range can be
designated for read access only.
Ø Programmable access protection — Each chip select address range can be
designated for supervisor access only.
Ø Write-enable selection — The enable byte pins (EB [3:0]) can be configured as
byte enables (assert on both external read and write accesses) or write enables
(only assert on external write accesses).
Ø Bus cycle termination — The chip select logic to terminate the bus cycle.
Ø Programmable wait states — To interface with various devices, up to seven wait
states can be programmed before the access is terminated.
Ø Programmable extra wait state for write accesses — One wait state can be added
to write accesses to allow writing to memories that require additional data setup
time.

memory integration Datasheet.rar