This IP core implements a flexible controller for NAND flash memory devices from 2 to 128 Gb (single device). A smaller controller for up to 2 Gb NAND Flash devices is also available.

The full-featured NAND flash controller core efficiently manages the read/write interactions between a master host system and Single- or Multi-Level Cell (SLC or MLC) NAND flash memory devices. The core includes an optional direct memory access (DMA) manager, uses a comprehensive command set for easy NAND Flash memory access, automatically remaps corrupted memory blocks to improve reliability, can protect memory areas against writes with a block lock mode, has built-in power-saving features, and can boot software directly from Flash memory.

The controller works with any suitable memory device with 2- or 4-kB page sizes supporting the Open NAND Flash Interface Working Group (ONFI) 1.0 standard.

The NAND Flash Controller employs a standard OCP 2.0 socket interface to facilitate easy adaption into all types of design structures depending on the designer needs. OCP is being widely adopted due to its ease of integration and flexibility. A wrapper supporting AMBA 2 AHB master and slave buses is available and other structures are available by request.

The Controller offers two error code correction (ECC) mechanisms from the relatively simple single-bit Hamming Code to more sophisticated high-speed BCH (Bose, Ray-Chaudhuri and Hocquenghem) ECC. BCH targets applications with high-density memory as well as direct boot from the NAND flash device.