The AU-M1000 SRAM Controller Core is a versatile, pipelined, high performance SRAM
controller. Several SRAM types are supported including flow through ZBT synchronous
SRAMs, pipelined ZBT synchronous SRAMs, flow through syncburst synchronous SRAMs,
SCD syncburst synchronous SRAMs, DCD syncburst synchronous SRAMs, and asynchronous
SRAMs. The SRAM Controller supports SRAM memory systems from 512 Kbytes to 512
Mbytes. The SRAM data bus width is user configurable to 32 or 64 bits. To conserve power the
SRAMs can be put in low power mode. The SRAM Controller is available as a synthesizable
Verilog model from Aurora VLSI, Inc.

• Supports several SRAM types- flow through ZBT synchronous, pipelined ZBT
synchronous, flow through syncburst synchronous, SCD syncburst synchronous,
DCD syncburst synchronous, and asynchronous SRAMs
• 32 bit or 64 bit SRAM data bus
• 512 Kbyte to 512 Mbyte SRAM memory system
• Pipelined accesses for highest performance
• 0, 1, or 2 cycle read latency
• 0, 1, or 2 cycle write latency
• 1, 2, or 4 banks of SRAM
• 17 to 24 address bits
• SRAM powerdown supported