The AU-M2200 SDRAM/DDR Controller Core is a pipelined, high performance SDRAM and
DDR SDRAM controller. Software configures the SDRAM/DDR Controller for either SDRAM
or DDR SDRAM accesses. The SDRAM/DDR SDRAM data bus width is user configurable to
32 or 64 bits. The SDRAM/DDR Controller supports SDRAM and DDR SDRAM memory
systems from 4 Mbytes to 4 Gbytes. SDRAM/DDR SDRAM timing parameters are software
programmable to support a wide range of SDRAM and DDR SDRAM speed grades and clock
frequencies. Refresh is initiated by the SDRAM/DDR Controller according to the software
programmable refresh interval. To conserve power the SDRAM/DDR SDRAMs can be put in
low power mode. The SDRAM/DDR Controller is available as a synthesizable Verilog model
from Aurora VLSI, Inc.

• 32 bit or 64 bit SDRAM/DDR SDRAM data bus
• 4 Mbyte to 4 Gbyte SDRAM/DDR memory system
• Pipelined accesses to active rows for highest performance
• 1, 2, or 4 banks of SDRAM/DDR SDRAMs
• SDRAM/DDR SDRAM powerdown supported
• Fully programmable SDRAM/DDR SDRAM timing parameters
• Auto-refresh with programmable SDRAM/DDR SDRAM refresh interval
SDRAM
• 2 or 3 cycle CAS latency
• 2 or 4 SDRAM internal banks
• 8, 9, 10, 11, or 12 column address bits
• 11, 12, or 13 row address bits
DDR
• 2, 2.5, or 3 cycle CAS latency
• 4 DDR SDRAM internal banks
• 9, 10, 11, or 12 column address bits
• 12, 13, or 14 row address bits