The AU-M2020 DDR2 Controller Core is a pipelined, high performance DDR2 SDRAM
controller. The DDR2 SDRAM data bus width is user configurable to 32 or 64 bits. The DDR2
Controller supports DDR2 SDRAM memory systems from 4 Mbytes to 4 Gbytes. DDR2
SDRAM timing parameters are software programmable to support a wide range of DDR2
SDRAM speed grades and clock frequencies. Refresh is initiated by the DDR2 Controller
according to the software programmable refresh interval. To conserve power the DDR2
SDRAMs can be put in low power mode. The DDR2 Controller is available as a synthesizable
Verilog model from Aurora VLSI, Inc.

• 32 bit or 64 bit DDR2 SDRAM data bus
• 4 Mbyte to 4 Gbyte DDR2 memory system
• Pipelined accesses to active rows for highest performance
• 3, 4, or 5 cycle CAS latency
• 1, 2, or 4 banks of DDR2 SDRAMs
• 4 or 8 DDR2 SDRAM internal banks
• 9, 10, 11, or 12 column address bits
• 13 or 14 row address bits
• DDR2 SDRAM powerdown supported
• Fully programmable DDR2 SDRAM timing parameters
• Auto-refresh with programmable DDR2 SDRAM refresh interval