The AU-MB2020 DDR2 Controller AMBA Subsystem provides a DDR2 Controller peripheral
subsystem for AMBA based SOCs. It contains a DDR2 Controller that connects seamlessly to
the AMBA AHB Bus as an AMBA Bus slave. The DDR2 Controller AMBA Subsystem Core is
available as a synthesizable Verilog model from Aurora VLSI, Inc.

DDR2 Controller
• 32 bit or 64 bit DDR2 SDRAM data bus
• 4 Mbyte to 4 Gbyte DDR2 SDRAM memory system
• Pipelined accesses to active rows for highest performance
• 3, 4, or 5 cycle CAS latency
• 1, 2, or 4 banks of DDR2 SDRAM
• 4 or 8 DDR2 SDRAM internal banks
• 9, 10, 11, or 12 column address bits
• 13 or 14 row address bits
• DDR2 SDRAM powerdown supported
• Fully programmable DDR2 SDRAM timing parameters
• Auto-refresh with programmable DDR2 SDRAM refresh interval
AMBA Slave Interface
• AMBA AHB Bus slave
• 32 bit or 64 bit AMBA AHB Bus- user configurable
• Supports all required AMBA AHB Bus features
• Implements AMBA Bus timeout and RETRY response
• Read data prefetching
• Write data packing
• Same cycle device request/response is supported for highest throughput
• Handles all data packing/unpacking and data alignment for data transfer sizes that do
not match the AMBA Bus width and/or DDR2 SDRAM data bus width
• User configurable for big or little endian AMBA Bus and memory
• AMBA Bus and DDR2 SDRAM interface can be asynchronous to each other