The AU-MB2001 SDRAM Controller AMBA Subsystem provides a three port SDRAM
Controller peripheral subsystem for AMBA based SOCs. It contains an SDRAM Controller that
connects seamlessly to the AMBA AHB Bus as an AMBA Bus slave, and also has two additional
generic SDRAM request ports. The SDRAM Controller AMBA Subsystem Core is available as a
synthesizable Verilog model from Aurora VLSI, Inc.

SDRAM Controller
• 32 bit or 64 bit SDRAM data bus
• 4 Mbyte to 4 Gbyte SDRAM memory system
• Pipelined accesses to active rows for highest performance
• 2 or 3 cycle CAS latency
• 1, 2, or 4 banks of SDRAM
• 2 or 4 SDRAM internal banks
• 8, 9, 10, 11, or 12 column address bits
• 11, 12, or 13 row address bits
• SDRAM powerdown supported
• Fully programmable SDRAM timing parameters
• Auto-refresh with programmable SDRAM refresh interval
AMBA Slave Interface
• AMBA AHB Bus slave
• 32 bit or 64 bit AMBA AHB Bus- user configurable
• Supports all required AMBA AHB Bus features
• Implements AMBA Bus timeout and RETRY response
• Read data prefetching
• Write data packing
• Same cycle device request/response is supported for highest throughput
• Handles all data packing/unpacking and data alignment for data transfer sizes that do
not match the AMBA Bus width and/or SDRAM data bus width
• User configurable for big or little endian AMBA Bus and memory
• AMBA Bus and SDRAM interface can be asynchronous to each other
Generic Requester Interfaces
• 2 generic SDRAM requester interfaces
• 64 bit data
• Request/ready protocol to issue an SDRAM request
• Data valid/ready protocol to transfer data
• Round robin arbitration between each Generic Requester Interface and the AMBA
Slave Interface