The AU-M5000 XD Controller Core is a versatile XD module controller that supports various
sizes of XD modules from 16 Mbytes to 8 Gbytes. The XD Controller data bus width is user
configurable to 8, 16, or 32 bits. The XD Controller supports XD memory systems from 16
Mbytes to 128 Gbytes. XD module timing parameters are both user configurable at reset with
Verilog parameters and software programmable to support a wide range of XD module speed
grades and system clock frequencies. The XD Controller is available as a synthesizable Verilog
model from Aurora VLSI, Inc.

• 1, 2, or 4 banks of XD modules
• 8 bit, 16 bit, or 32 bit XD Controller data bus
• 16 Mbyte to 128 Gbyte XD memory systems
• User configurable reset values and fully programmable XD module timing
parameters
• Read, Program, Erase, Read Status, Read Status2, Read ID, Read ID2, Read ID3, and
Reset commands
• 16 Mbyte to 8 Gbyte XD modules- configurable
• 512 byte or 2048 byte page size- configurable
• ECC hardware support
• spare area usage- configurable
• Interrupt or host processor polling for XD command completion