The AU-MB3001 Flash Controller AMBA Subsystem provides a Flash Controller peripheral
subsystem for AMBA based SOCs. It contains a Flash Controller that connects seamlessly to the
AMBA AHB Bus as an AMBA Bus slave. The Flash Controller AMBA Subsystem Core is
available as a synthesizable Verilog model from Aurora VLSI, Inc.

Flash Controller
• NAND and NOR flash controller
• 1, 2, or 4 banks of flash chips
• 8 bit, 16 bit, 32 bit, or 64 bit Flash Controller data bus
• 8 Mbyte to 512 Gbyte NAND flash memory systems
• 512 Kbyte to 1 Gbyte NOR flash memory systems
• User configurable reset values and fully programmable flash chip timing parameters
• NAND flash (SLC and MLC)
- Read, Program, Erase, Read Status, Read ID, Copy Back, and Reset
- Other NAND flash commands using Direct Read and Direct Write
- ONFI industry standard command compatible
- 64 Mbit to 256 Gbit flash chips- configurable
- 8 bit or 16 bit flash chip data bus- configurable
- 512 byte, 2048 byte, or 4096 byte page size- configurable
- ECC generation and correction
- spare area usage- configurable
- 2, 4, or 5 cycle ID register read- configurable
• NOR flash
- Read, Program, Erase, Read Status, Read ID, Read CFI, Clear Status,
Buffered Write, Lock, Unlock, and Lock Down
- Other NOR flash commands using Direct Read and Direct Write
- NOR flash RP/RST/RESET (reset) assertion by the Flash Controller
Subsystem reset input port
- 4 Mbit to 512 Mbit flash chips- configurable
- 8 bit or 16 bit flash chip data bus- configurable
- 64 Kbyte or 128 Kbyte main block size- configurable
- top, bottom, or no boot block- configurable
- 8 Kbyte, 16 Kbyte, or 32 Kbyte boot block size- configurable
• Interrupt or host processor polling for flash command completion
AMBA Slave Interface