类型:软IP
简短描述:Flash Controller Core
详细描述:
The AU-M3001 Flash Controller Core is a versatile NAND/NOR flash controller that supports
various types of NAND and NOR flash chips from several manufacturers. The Flash Controller
data bus width is user configurable to 8, 16, 32 or 64 bits. The Flash Controller supports NAND
flash memory systems from 8 Mbytes to 512 Gbytes, and NOR flash memory systems from 512
Kbytes to 1 Gbyte. Flash chip timing parameters are both user configurable at reset with Verilog
parameters and software programmable to support a wide range of flash speed grades and system
clock frequencies. The Flash Controller is available as a synthesizable Verilog model from
Aurora VLSI, Inc.
工艺:
代工厂:
应用:
特色:
• NAND and NOR flash controller
• 1, 2, or 4 banks of flash chips
• 8 bit, 16 bit, 32 bit, or 64 bit Flash Controller data bus
• 8 Mbyte to 512 Gbyte NAND flash memory systems
• 512 Kbyte to 1 Gbyte NOR flash memory systems
• User configurable reset values and fully programmable flash chip timing parameters
• NAND flash (SLC and MLC)
- Read, Program, Erase, Read Status, Read ID, Copy Back, and Reset
commands
- Other NAND flash commands using Direct Read and Direct Write
- ONFI industry standard command compatible
- 64 Mbit to 256 Gbit flash chips- configurable
- 8 bit or 16 bit flash chip data bus- configurable
- 512 byte, 2048 byte, or 4096 byte page size- configurable
- ECC hardware support
- spare area usage- configurable
- 2, 4, or 5 cycle ID register read- configurable
• NOR flash
- Read, Program, Erase, Read Status, Read ID, Read CFI, Clear Status,
Buffered Write, Lock, Unlock, and Lock Down
- Other NOR flash commands using Direct Read and Direct Write
- NOR flash RP/RST/RESET (reset) assertion by the Flash Controller reset
input port
- 4 Mbit to 512 Mbit flash chips- configurable
- 8 bit or 16 bit flash chip data bus- configurable
- 64 Kbyte or 128 Kbyte main block size- configurable
- top, bottom, or no boot block- configurable
- 8 Kbyte, 16 Kbyte, or 32 Kbyte boot block size- configurable
• Interrupt or host processor polling for flash command completion