Implements a controller providing a simple, flexible, burst-optimized interface to all in-dustry-standard single data rate (SDR) Mobile and ordinary SDRAM memory devices. Also works with registered/unbuffered DIMMs. It supports up to a 2G (2³⁰ word) memory address space, provides up to eight chip selects, and manages up to four memory banks.

The core automatically handles memory management, initialization, and refresh operations. It gives the user a simple command interface, hiding details of the required address, page, and burst handling procedures. All memory parameters are runtime-configurable, including timing (CAS Latency, tRP, etc.), memory setting (Row Bits, Column Bits, etc.), and Mobile-SD and Extended-Mode-Register settings. A configurable auto-close mechanism precharges inactive memory banks to minimize power dissipation, and configurable power-down and self-refresh features plus support for sleep mode help reduce power consumption.

The flexible user interface features separate read and write ports, and the core handles single word accesses as well as arbitrary-length bursts, emulating a linear memory space with no page or bank boundaries. A pipelined design achieves maximum memory bandwidth utilization, while parallel state machine design practices further improve performance. The rigorously-verified core is silicon-proven and has been embedded in several products. It offers very competitive implementation characteristics, requiring for example just 9,400 gates and running at 200 MHz in a typical .18 micron ASIC process.