类型：软IP
简短描述：ESSINCOS1601是一种采用面向于ASIC的，用可综合的Verilog HDL语言风格进行设计的基于CORDIC算法的迭代结构设计的实现计算Sin Cos功能的IP软核。
详细描述：
The ESSINCOS1601 core is the Verilog HDL synthesizable model to implement the function of calculating sine cosine.The core is a digital signal processing block, working on 16 bits of data at a time. The whole calculation process are performed in 24 clocks. The design uses the iterative structure,so the area of the core is very small.The core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The core is available optimized for several technologies with competitive utilization and performance characteristics.
工艺：
代工厂：
应用：
特色：
Using CORDIC algorithm;
Simple interface and timing
Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
Iterative structure
Small gate count
The whole calculation process are performed in 24 clocks
SinCos01_eSolutions.rar
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