类型：软IP
简短描述：USB 1.1 Hub Core
详细描述：
The SSU8040 USB 1.1 Hub Core provides USB 1.1 Hub functionality. The USB 1.1 Hub Core
is available as a synthesizable Verilog model from Aurora VLSI, Inc.
工艺：
代工厂：
应用：
特色：
• Fully synchronous design
• All signals are registered on the rising edge of the system clock
• Supports four ports, modifiable to more ports
• Handles all USB standard requests and hub class specific requests
• Handles EPO transfers for command decodes
• Has EP1 handler for port status reporting
• Can be used as a compound device, to perform bulk, isochronous transfers
• Connect/disconnect detection
• Suspend/resume logic
• Reset ports, enable ports, and disable ports
• EOF1, EOF2 and frame boundary conditions are handled in the core
• Has a simple memory interface for configuration management
您当前的位置：
