The SSF8010 is the Link Layer Controller for IEEE 1394a. It is a fully synthesizable core, which
can be integrated seamlessly with any application. The SSF8010 interfaces to the PHY Chip
using the IEEE 1394a-2000 PHY standard and IEEE 1394-1995 Annex J PHY standard. On the
application side, a simple interface provides direct access to receive and transmit FIFOs. The
SSF8010 supports 100, 200 and 400 Mbits/s transfers. The 1394a LLC Core is available as a
synthesizable Verilog model from Aurora VLSI, Inc.

• Compliant with IEEE 1394a
• SSF8010 has link layer functionality
• Uses IEEE 1394a-2000 PHY standard and IEEE 1394-1995 Annex J PHY standard
to interface to the PHY chip
• Asynchronous and isochronous transfers are supported
• Supports 100, 200, and 400 mbits/s
• Simple application interface
• Direct FIFO access for both asynchronous and isochronous interface
• Cycle master capability
• Generates CRC for transmit and checks CRC for receive packets
• Separate FIFOs for transmitting asynchronous and isochronous packets