The AU-SB1000 Processor Memory and AMBA Bus Interface Core provides system interfaces
for Aurora VLSI processors including the AU-C01XX Processor Core family and AU-JXXXX
Java Core family, in AMBA based SOCs. In an SOC, it connects the Processor Core to the
memory system that may include RAM, an AMBA AHB Bus, and on-chip configuration, control,
and status registers. The AU-SB1000 Processor Memory and AMBA Bus Interface Core is
available as synthesizable Verilog models from Aurora VLSI, Inc.

Processor Memory and Bus Interface
• Memory and bus interface supporting Aurora VLSI Processor Cores
- AU-C01XX 32 Bit, Tiny, Low Power Processor Cores
- AU-JXXXX Java Processor Cores
• Seamless connection to Aurora VLSI Processor Cores
• Memory system requests from the Processor Core on two independent request
interfaces
- instruction request interface
- data request interface
• Determines the memory request target:
- RAM memory
- AMBA Bus peripheral device
- On-chip register
• Drives the request to the memory request target
• Receives read data and error information from the request target
• Passes read data and error information back to the Processor Core
• Signals memory system wait cycles to the Processor Core as needed
AMBA Bus Master
• 32 bit or 64 bit AMBA AHB Bus- user configurable
• Fully pipelined for highest throughput
• Supports all required AMBA AHB Bus features
• AMBA Bus read error returned to the user with the read data