The AU-S3000 DMA Engine Core provides Direct Memory Access (DMA) functionality that
moves blocks of data between main memory and peripheral bus devices, and between areas in
main memory. Both the main memory interface and the bus interface are generic. The main
memory interface will typically connect to a block such as an SDRAM controller. A bus master
that supports the chosen system bus will typically connect to the bus interface. Up to eight
independent DMA channels are supported. The AU-S3000 DMA Engine Core is available as a
synthesizable Verilog model.

• 1 to 8 channels- user configurable
• DMA between
- bus devices and RAM memory
- two memory areas in RAM memory
• Physical DMA
• Programmable source starting address
• Programmable destination starting address
• Programmable transfer count- up to 64 Kbytes
• Programmable bus interface transaction size- 8 to 32 Kbytes
• Programmable bus data transfer size- 1, 2, 4, or 8 bytes
• Memory interface transaction size optimized for RAM burst operations
• Locked DMA operation optional (software programmable)
• Direct software writes or information extracted from descriptors in memory, to
program DMA control information
• Scatter/gather DMA using a chained descriptor list in memory as the DMA control
information source
• Host processor initiates the DMA operation
• Interrupts signal the end of DMA operations
• Several error types end DMA operations, are recognized and logged
• 64 bit data width at the memory and bus interfaces
• Dedicated bus interface for each DMA channel
• Shared memory interface
• Round robin arbitration for the shared memory interface
• Bus device can optionally determine transfer count and start of the DMA operation
• Request/acknowledge handshake with bus slaves for most efficient bus usage