Implements a high-speed (10/100 Mbps), half- and full-duplex LAN controller using the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media access control over the Ethernet.

For broad compatibility and easy integration, the core works with any MII-compliant external PHY transceiver. (SMII & RMII support is available.)

The core has a generic host-side interface designed for easy compatibility with a variety of external CPUs or standard bus controllers such as PCI. This host interface can be configured to work with 8-, 16- or 32-bit data bus lengths with big or little endian byte ordering, and is compatible with most modern virtual component interfaces. Optional standard interfaces such as AMBA, OCP, and OPB are available.

The MAC was developed for reuse in ASIC and FPGA implementations and has been implemented in several commercial products. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.