The SideWorks Low Latency Mixed-Radix FFT/IFFT (CWfftmrll08) is part of the SideWorks™ family of proven DSP kernel cores and performs complex FFT/IFFT computations for various block sizes with minimal latency at the cost of extra hardware. The block size is configurable and can be set by means of a control register, which is also used to start the computation.  The block start signal can be monitored to know when the computation is ready. The blocks to be processed, as well as the computed frequency coefficients, can be read from the block’s internal memory, which is optionally memory mapped on the system’s bus interface (AMBA, CoreConnect, or others). This IP block is implemented using the Coreworks proprietary SideWorks™ DSP engine technology, which ensures small silicon area, low power and rapid development time.

• 20 uS processing time @ 250 MHz for worst case FFT size (150MS/s)
• Runtime configurable FFT size and factorization
• FFT of any size from 2 to 1536 points (factorized by 2,3 and 5)
• Supports 2, 3, and 5 FFT radix factors
• 16 bit sample width
• 32 bit bus interface
•  Latency equals N + 5% in worst case scenario (N=FFT number of points)
• Four blocks of 1536x16bit data RAM
• Two blocks of 1536x16bit coefficients and code ROM
• Optional flexible interface: AMBA®, CoreConnect™ or others (eg. simply parallel with REQ/ACK handshaking)
• Natural input / output order