This PLL is designed for audio clock generation. The reference clock is either 12MHz crystal or the input clock. It supports 256*fs clock output, where fs is the audio system sample rate of 32kHz/44.1kHz/48kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.

Process: SMIC 0.13um Logic 1P6M 1.2V/3.3V CMOS process 
Supply voltage: 3.3v +/-10%; 1.2v+/-10% 
Reference input: 12MHz crystal or external clock 
Clocks output: 12.286MHz, 11.294MHz, 8.190MHz,6.143MHz, 5.647MHz, 4.095MHz, 3.071MHz, 2.823MHz, 2.048MHz 
Output duty cycle: 49~51% 
Current: <1.5mA 
Operating temperature: 0~85°C