The DES core implements the Data Encryption Standard (DES) documented in the U.S. Government publication FIPS 46-3.

The DES core is a block cipher, working on 64 bits of data at a time.  The DES core uses a single 64 bit key of which only 56 bits are used. Encoding and decoding operations are performed in 16 clocks per block, in Electronic Codebook (ECB) mode.

The DES core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs.  The DES IP Core is delivered as Verilog RTL Source code.

This DES Core non-pipelined version is implemented to minimize the gate count and FPGA resources. After an initial latency of 16 cycles, it can output encryption/decryption at every cycle. The design does not use any memories such as SRAM. 

The DES core pipelined version is implemented to maximize performance by pipelining the DES transformation algorithm.  The design does not use any memories such as SRAM

• FIPS 46-3 Standard Compliant
• Encryption/Decryption performed in 16 cycles 
  (ECB mode)
• 56 bits of security
• For use in FPGA or ASIC designs
• Verilog IP Core

cast_des.rar