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| Silicon Image, Inc:Video Decoder IP Core |
类型：软IP
简短描述：cineramIC-4K/3D FPGA Multi-Standard Ultra High-Definition Video Decoder IP Core
详细描述：
The cineramIC-4K/3D FPGA Multi-Standard Ultra High-Definition Video Decoder IP core supports H.264, MPEG-1/2 and VC-1 video standards including H.264 MVC (Multiview Video Coding) and JPEG standards for still picture applications. Automatic multi-stream video decoding is supported for up to 16 streams without additional software interaction. The scalable architecture supports FPGA implementations by reducing the clock frequency to function in an FPGA environment. Driver software performs set up and general controlling tasks requiring fewer than 2 MIPS of CPU resources on common general purpose 32-bit processors.
工艺：
代工厂：
应用：
特色：
ITU-T H.264 incl. Annex H, MVC, ISO/IEC 14496-10 (Main and High Profile up to Level 5.1)
SMPTE 421M VC-1 (Simple, Main and Advanced Profile @ Level 4)
ISO/IEC 11172-2 MPEG-1
ISO/IEC 13818-2 MPEG-2 (Main Profile @ High Level)
Supports up to 4096 x 2160 pixel resolutions(4Kx2K)
Supports 3D video
Supports Exif JPEG up to 16Kx8K picture size
Supports all DVTB, ATSC, HDTV, DVD, VCD resolutions (e.g. 1080p, 1080i, 720p, D1)
Hardware supported context switching between video streams (configurable up to 16 streams)
Error detection and concealment
Trick mode support
Processing of ES and PES streams, extraction and provision of time stamps
FPGA core and memory system can run with different clocks; clock domain crossing is part of the IP core
Implementation for ASIC SoC available
Allegro H.264 certification test suite proven
64-bit ports to memory system, OCP 2.0 and AMBA AXI compliant
Runs on FPGAs such as Altera Stratix III/IV or Xilinx Virtex 5/6
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  Silicon Image, Inc:Video Decoder IP core |
 IPGoal:Audio CODEC |
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