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| Silicon Image, Inc:camerIC - 18 |
类型：软IP
简短描述：Camera Processor IP Cores up to 18 Megapixels
详细描述：
The camerIC-18 camera processor IP cores are a complete 18 megapixel (MP) video and still picture input unit designed for SoCs providing image capture capability in mobile phones, Portable Media Players (PMPs) and netbooks with integrated cameras. The high-performance camera pipeline features image processing, scaling and compression functions. The integrated image signal processor (ISP) supports simple CMOS sensors with no image pre-processing and sensors with integrated YCbCr processing.
The camerIC-18 IP core is Silicon Image’s fifth generation family of camera processor IP cores. Since 2002, over 20 camera designs have been delivered for use in System-on-a-Chip (SoC) application processors for digital still cameras, mobile phone and netbooks.
Applications: Digital Still Cameras & Camcorders , Mobile Phones/Cameras , Notebook PCs , Portable Multimedia Players
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特色：
12-bit camera interface for (RGB Bayer input)
MIPI & SMIA serial input interface
Maximum input resolution up to 18 Megapixel (4928 x 3696)
Advanced bad pixel detection and correction on the fly
Lens shade correction (vignetting)
Video image stabilization support
Auto focus measurement
Auto white balancing
Auto exposure support by brightness measurement
Histogram calculation
Flash light control
Mechanical shutter support
Black level compensation
Enhanced color interpolation (RGB Bayer demosaicing)
Sharpening / blurring / noise filter
Color correction matrix (cross talk matrix)
Super impose, digital zoom & continuous resize support
Wide Dynamic Range Processing (Tone mapping)
ITU-R BT.601 & 656 compliant video interface
HW JPEG encoder including JFIF1.02 stream generator with programmable quantization and Huffman tables
Display-ready RGB output in self-picture path
Rotation in 90° steps for display-ready RGB output
Max. 300 MHz system & max. 300 MHz sensor clock
YCbCr 4:2:2 and 4:2:0 processing
Frame skip support for video encoding (e.g. MPEG-4)
Format conversion between YCbCr 4:2:2, 4:2:0, 4:1:1 and 4:1:0 formats
Planar and semi-planar storage format for YCbCr
ARM AMB AAHB 32-bit and ARM AMB AAXI 64-bit interfaces to system memory supporting up to 16 beat burst length
Power management by software-controlled clock disabling for currently not needed submodules
Additional features are available on request
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 Silicon Image, Inc:camerIC - 18 |
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