This design serves both as I²C compatible master and slave. It has two state machines,first is the main state machine which is same for either master or slave , while second is responsible for generating clock signal in master mode. These state machines have been interface with a module which is used for decoding the commands from processor. On top of these, a module has been created which actually interfaces with the processor. The communication between design  and processor follow the Wishbone protocol.

•   Both Master and slave operation
•   Both Interrupt and non interrupt data-transfers
•   Start/Stop/Repeated Start generation
•   Fully supports arbitration process
•   Software programmable acknowledge bit 
•   Software programmable time out feature
•   programmable address register
•   Programmable SCL frequency
•   Soft reset of I2C Master/Salve
•   Programmable maximum SCL low period
•   synthesis core
• i2c_master_slave_core.rar