类型:Hard IP
简短描述:Tri-Mode Television IF Subsystem. Silicon IP with Sigma-Delta Modulator ADC and Mixer for CMOS
详细描述:
The Tri-Mode Television IF Subsystem IP is designed to operate in television tuner systems that use Orthogonal Frequency Division Multiplexing with either Zero IF/Quadrature Baseband (0 +/- 4MHz), High IF/Real Bandpass (36.1 +/- 4MHz) signals or Low IF/Quadrature baseband (5.7 +/- 4MHz) input signals.
The heart of the subsystem is an Intrinsix Sigma-Delta Modulator (SDM) based analog to digital converter (ADC) to convert the analog input signal into a 10-bit I & Q digital bit stream.
In the Zero-IF mode, the system accepts a baseband quadrature input signal (0 +/- 4MHz) and generates a 1-bit quadrature SDM output bit stream at 243.2 MHz centered with an IF of 5.7MHz. The frequency content of the SDM output bit stream is 5.7 +/- 4MHz.
In the High-IF mode, the input to the system is changed to a real bandpass signal (36.1 +/- 4MHz). In this mode, the in-phase and quadrature inputs to the system are tied together to the real bandpass signal to avoid any signal loss. The SDM again produces a quadrature 1-bit stream of data at 243.2MHz with a center frequency of 5.7MHz as in the ZIF case.
In the Low-IF mode, the input to the system is a quadrature input signal at 5.7 +/- 4MHz which is input directly into the SDM by using DC LO signals in the mixer. The SDM produces a quadrature 1-bit data stream at 243.2MHz with the same 5.7MHz center frequency. For more information on the Low-IF mode, please contact Intrinsix.
In all three modes the digital bit stream from the SDM is fed to a DSP block for decimation. The IP is currently targeted to a CMOS 130ηm process.
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Tri-mode IF (Zero, Low, High)
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CMOS process for low cost, low power design
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10-bit digital output
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Integrated mixer
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Self calibrating Sigma-Delta Modulator based ADC for high precision data conversion