The Intrinsix Sigma-Delta Stereo ADCs for Cost Effective Conversions (SD-ADC-CEC) are part of the larger offering of Sigma-Delta IP available from Intrinsix. 

 The family of SD-ADC-CEC is generated utilizing proprietary, patent-pending techniques within the Intrinsix SDM Refinery toolset.  A design methodology that is geared towards a digital CMOS process helps reduce cost, die size and power consumption.  A high Signal to Noise Ratio (SNR) is achieved by pushing the frequency of the quantization noise outside the band of interest.  The challenge in Sigma-Delta ADC design is the "shaping" of this noise, which is characterized by the Noise Transfer Function (NTF), and the design of efficient filters to attenuate the noise.  The SDM Refinery automates this process:  The engineer specifies an Over-Sampling Ratio (OSR), quantization levels, order of complexity and SDM Refinery creates the desired ADC.

    Available in 16 and 20-bit resolutions

    Available in 3rd and 4th Order  SD Modulation Complexity

       (others available upon request)

    Able to achieve a Signal-to-Noise Ratio (SNR) of 105db

   Compact design resulting in small die area

   Very low in power consumption with a customizable Low Power Mode

    Highly tunable for each application

    Available as RTL and GDSII as well as RTL and Behavioral System models in industry

       standard formats such as Verilog-A or Simulink