This PLL is designed for audio clock generation. The reference clock is 12MHz crystal or the input clock. It supports 256*fs clock output, where fs is the audio system sample rate of 32kHz/44.1kHz/48kHz. It integrates a phase frequency detector (PFD), a loop filter (LP), a voltage control oscillator (VCO), a current reference, two programmable dividers and other supportive circuits.

Process: SMIC 0.18um 1P4M mixed-signal process with MIM capacitor  
Supply Voltage: 3.3v+/-10%; 1.8v+/-10%  
Reference Input: 12MHz crystal or external clock  
Clock Output: 12.286MHz, 11.294MHz, 8.190MHz, 6.143MHz, 5.647MHz, 4.095MHz, 3.071MHz, 2.823MHz, 2.048MHz  
Output Duty Cycle: 49~51%  Current: <1.5mA  
Operating Temperature: 0~85癈