VeriSilicon SMIC 0.18um 1.8V/3.3V Clockgating Cell (01) Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8/3.3V process. This library supports both latch posedge and latch negedge type clock gating cell and with/without postcontrol test function with multiple drive strengths. While satisfying the performance and power requirements, it was optimized for area efficiency.

SMIC 0.18um Logic 1P6M Salicide 1.8V/3.3V process 
Supports posedge and negedge type clock gating cells.  
Supports post-control test function. 
Supports multiple drive strengths. 
Suitable for four, five and six layers of metal.