The USB2.0 OTG PHY is a complete intellectual property (IP) solution, integrating high-speed mixed-signal CMOS circuitry, and is designed for single-chip, USB2.0 integration in OTG application. The PHY supports the USB2.0 high-speed protocol at 480-Mbps (high-speed), and is backward compatible to the USB1.1 legacy protocol at 12M-bps (full-speed) and 1.5-Mbps (low-speed). The PHY抯 flexible architecture can be connected with a HS OTG subsystem to perform as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a fully USB2.0 Hi-Speed compliant peripheral or an OTG host. For example, when the USB2.0 OTG PHY is implemented in a USB printer, the printer can print from a PC, or the printer can act as the host, extracting and printing pictures directly from the memory of a digital cameral without the aid of a PC. Additional applications includes PDAs, mobile phones, MP3 player, set-top boxes, and fax machines.

Fully complies with: Universal Serial Bus Specification Rev 2.0 ON-THE-GO SUPPLEMENT TO THE USB 2.0 SPECIFICATION REV 1.0A UTMI+ Specification Rev 1.0 (Level 3)  
Complete mixed-signal physical layer (PHY) for single-chip USB2.0 OTG applications  
Supports 480Mbit/s 揌igh Speed? 12Mbit/s 揊ull Speed? 
USB2.0 Device automatic switching between full- and high-speed modes  
USB2.0 Host automatic switching between low-, full- and high-speed modes  
8-bit interface at 60MHz operation and 16-bit interface at 30MHz operation  
Supports Suspend, Resume and Remote Wakeup modes 
12MHz external crystal, plus an internal oscillator and 480MHz PLL  
All required terminations are internal to the PHY  
Supports USB2.0 test mode  
Additional built-in analog testability features 
Bist function and internal loop function for test  
Supports built-in and external source of VBUS  
Output current of the built-in charge pump adjusted by an external capacitor