The Verisilicon S13_ADC_03 IP is a 10 bits, low power, and pipeline analog to digital converter capable of running at up to 20MHz conversion rate. The ADC cell integrates several stages of sample/hold amplifiers, a reference bias circuit, and a clock circuit along with the analog to digital converter circuit. The S13_ADC_03 operates when the power-down signal (PWDN) is at logic level ?? and goes into power-down state when the power-down signal is at logic level ?? The S13_ADC_03 IP is useful in a variety of data signal conversion applications, especially in video applications.

Process: SMIC 0.13um 1P6M CMOS Generic process  Supply voltage: 1.2V analog/digital power, 1.2 V digital power  
Operating temperature: -10c ~ +60c ~ +120c Typical power dissipation: about 40mw(33mA), of which about 5mA is for digital power whereas 28mA for analog power  
The sampling network of sample/hold stage has been optimized for wider input bandwidth (up to 40MHz)  
Control pin is provided for power-down mode  
Fully differential structure  
Sampling rates: up to 20MHz