The S13_DLL_02 generates 4-channel fixed timing delay and provides 1-channel test mode for DDR SDRAM controller usage. It integrates a Voltage-Controlled Delay Line (VCDL), a Phase-Frequency Detector (PFD) and a Charge Pump (CP). The operating voltage ranges from 1.08V ~ 1.32V, and the operating junction temperature from -40℃ ~ 125℃. It can process input clock frequencies ranging from 100MHz ~ 200MHz (DDR-200 / 266 / 333 / 400). This IP can be used in DDR SDRAM controller to generate a delay of 20% of DQS period that is represented by the reference input clock (FREF) in the DQ data latch process.

Reference frequency ranges from 100 MHz to 200MHz for (DDR 200/266/333/400) 
Low jitter output 
4-channel outputs with a delay time of 20% of the period of FREF or DQS 
No external component required 
Rise time matches fall time on the output signal抯 edges 
False lock detection 
Lock in time: Less than 100us