The AU-M2210 DDR/DDR2 Controller Core is a pipelined, high performance DDR and DDR2
SDRAM controller. Software configures the DDR/DDR2 Controller for either DDR or DDR2
SDRAM accesses. The DDR/DDR2 SDRAM data bus width is user configurable to 32 or 64
bits. The DDR/DDR2 Controller supports DDR and DDR2 SDRAM memory systems from 4
Mbytes to 4 Gbytes. DDR/DDR2 SDRAM timing parameters are software programmable to
support a wide range of DDR and DDR2 SDRAM speed grades and clock frequencies. Refresh
is initiated by the DDR/DDR2 Controller according to the software programmable refresh
interval. To conserve power the DDR/DDR2 SDRAMs can be put in low power mode. The
DDR/DDR2 Controller is available as a synthesizable Verilog model from Aurora VLSI, Inc.

• 32 bit or 64 bit DDR/DDR2 SDRAM data bus
• 4 Mbyte to 4 Gbyte DDR/DDR2 memory system
• Pipelined accesses to active rows for highest performance
• 1, 2, or 4 banks of DDR/DDR2 SDRAMs
• DDR/DDR2 SDRAM powerdown supported
• Fully programmable DDR/DDR2 SDRAM timing parameters
• Auto-refresh with programmable DDR/DDR2 SDRAM refresh interval
DDR
• 2, 2.5, or 3 cycle CAS latency
• 4 DDR SDRAM internal banks
• 9, 10, 11, or 12 column address bits
• 12, 13, or 14 row address bits
DDR2
• 3, 4, or 5 cycle CAS latency
• 4 or 8 DDR/DDR2 SDRAM internal banks
• 9, 10, 11, or 12 column address bits
• 13 or 14 row address bits