The AU-M2010 DDR Controller Core is a pipelined, high performance DDR SDRAM controller.
The DDR SDRAM data bus width is user configurable to 32 or 64 bits. The DDR Controller
supports DDR SDRAM memory systems from 4 Mbytes to 4 Gbytes. DDR SDRAM timing
parameters are software programmable to support a wide range of DDR SDRAM speed grades
and clock frequencies. Refresh is initiated by the DDR Controller according to the software
programmable refresh interval. To conserve power the DDR SDRAMs can be put in low power
mode. The DDR Controller is available as a synthesizable Verilog model from Aurora VLSI, Inc.

• 32 bit or 64 bit DDR SDRAM data bus
• 4 Mbyte to 4 Gbyte DDR memory system
• Pipelined accesses to active rows for highest performance
• 2, 2.5, or 3 cycle CAS latency
• 1, 2, or 4 banks of DDR SDRAMs
• 4 DDR SDRAM internal banks
• 9, 10, 11, or 12 column address bits
• 12, 13, or 14 row address bits
• DDR SDRAM powerdown supported
• Fully programmable DDR SDRAM timing parameters
• Auto-refresh with programmable DDR SDRAM refresh interval