The AU-MB5000 XD Controller AMBA Subsystem provides an XD Controller peripheral
subsystem for AMBA based SOCs. It contains an XD Controller that connects seamlessly to the
AMBA AHB Bus as an AMBA Bus slave. The XD Controller AMBA Subsystem Core is
available as a synthesizable Verilog model from Aurora VLSI, Inc.

XD Controller
• 1, 2, or 4 banks of XD modules
• 8 bit, 16 bit, or 32 bit XD Controller data bus
• 16 Mbyte to 128 Gbyte XD memory systems
• User configurable reset values and fully programmable XD module timing
parameters
• Read, Program, Erase, Read Status, Read Status2, Read ID, Read ID2, Read ID3, and
Reset commands
• 16 Mbyte to 8 Gbyte XD modules- configurable
• 512 byte or 2048 byte page size- configurable
• ECC hardware support
• spare area usage- configurable
• Interrupt or host processor polling for XD command completion
AMBA Slave Interface
• AMBA AHB Bus slave
• 32 bit or 64 bit AMBA AHB Bus- user configurable
• Supports all required AMBA AHB Bus features
• Implements AMBA Bus timeout and RETRY response
• Read data prefetching
• Write data packing
• Same cycle device request/response is supported for highest throughput
• Handles all data packing/unpacking and data alignment for data transfer sizes that do
not match the AMBA Bus width and/or XD data bus width
• User configurable for big or little endian AMBA Bus and memory