类型：软IP
简短描述：ESUART01是一种采用面向于ASIC，用可综合的Verilog HDL语言风格进行设计的通用异步收发器（UART)IP软核。
详细描述：
The ESUART01 core is the Verilog HDL synthesizable model of industry standard 16450 Unive- -rsal Asynchronous Receiver / Transmitter(UART),which provides an interface between a micro- -processor and a serial communications channel. It performs serial-to-parallel conversion on data received from a serial device or other peripheral devices, and parallel-to-serial conversion on data received from the CPU.The ESUART01 receives and transmits data in a variety of configurations, including 5-,6-, 7-, or 8-bit data words; odd, even, or no parity; and 1, 1.5, or 2 stop bits.The ESU- -ART01 includes an internal baud rate generator and interrupt control.Developed for easy reuse in ASIC and FPGA applications, the ESUART01 is available optimized for several technologies with competitive utilization and performance characteristics.
工艺：
代工厂：
应用：
特色：
Simple interface and timing
Fully Synchronous design.
Full duplex operation
Even, odd, or no parity generation and detection
False frame detection
<p class="MsoNormal" style="margin: 0cm 0cm 0pt 21pt; text-indent: -21pt; mso-layout-grid-align: none; mso-list: l0 level1 lfo1; tab-st
UART_Controller_eSolutions
您当前的位置：
