The DDR2-SDRAM-CTRL core provides a simplified, pipelined, burst-optimized interface to all industry-standard DDR and DDR-II SDRAM devices currently available, including Mobile DDR SDRAMs. It features:

• Simplicity. All required management, initialization, address and burst handling procedures are done by the core. The control, write-data, and read-data paths are split, enabling higher performance and easier integration.
• Performance. The core achieves maximum bandwidth utilization through pipelined and parallel architectural design practices.
• Flexibility. All memory parameters (timing parameters, memory size parameters, mobile-DDR support, auto-refresh policies, etc.) are runtime configurable.
• Easier Integration. Most necessary related components—DDR/DDR-II Controller, data-path FIFOs, DLLs—come built into the core, and some FPGA versions even include a PHY.

The core has been carefully designed and rigorously verified, and is delivered with comprehensive documentation and a complete verification environment.

• Interfaces to all industry standard DDR and DDR-II SDRAM DIMMs and chips, including Mobile DDR SDRAMs.
• High-performance architecture, with a three-stage processing queue for maximum bandwidth utilization.
• Pipelined design facilitates integration and enables high clock rates.
• Includes power-down and self-refresh, critical for low-power applications.
• Datapath logic with small FIFOs, enables handshaking mechanism for enhanced performance and easier integration.
• Two different PHY implementations available: an advanced delayed-DQS capture mechanism with per-bit deskew, and a delayed-clock capture with dual-port synchronizing FIFO.
• Utilizes per-bank status monitoring.
• Incorporates a programmable auto-precharge mechanism.
• Incorporates a programmable automatic refresh policy.
• Supports up to eight chip-selects, up to eight banks per chip, twelve to fifteen row bits, and nine to twelve columns bits.
• Runtime-configurable parameters ensure flexibility: eleven timing parameters, CAS latency, Burst Length, Row bits, Column bits, Bank bits, number of CSs, Extended-Mode-Registers’ values, registered-DIMM support, power-saving and auto-precharge mechanism activation.
• Flexible user-interface, with split command, write-data and read-data paths. All paths support hand-shaking mechanisms.
• Multi-burst access support: access requests can have any size burst lengths from 1 to 65536; the core segments these into an appropriate number of SDRAM bursts.

cast-ddr2-sdram-ctrl.rar