The ESDES02 core is the Verilog HDL synthesizable model to implement the Data Encryption Standard (DES) documented in the U.S. Government publication FIPS 46-3.The core is a block cipher, working on 64 bits of data at a time. The core uses a single 64 bit key of which only 56 bits are used. The design uses the pipeline structure and does not use any memories such as SRAM,so the data processing speed is very high. After an initial latency of 19 cycles, it can output encryption/decryption at every cycle. The core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The core is available optimized for several technologies with competitive utilization and performance characteristics.

Simple interface and timing

Fully Synchronous design.

Pipeline structure

High performance,high data throughput

Encryption/Decryption performed in 1 cycle (ECB mode) after an initial latency of 19 cycles

56 bits of security