类型：软IP
简短描述：ESDES01是一种采用迭代结构设计的，用可综合的Verilog HDL语言风格进行设计的实现Data Encryption Standard (DES)加解密算法标准的IP软核。
详细描述：
The ESDES01 core is the Verilog HDL synthesizable model to implement the Data Encryption Standard (DES) documented in the U.S. Government publication FIPS 46-3.The core is a block cipher, working on 64 bits of data at a time. The core uses a single 64 bit key of which only 56 bits are used. Encoding and decoding operations are performed in 17 clocks, in Electronic Codebook (ECB) mode. The design uses the iterative structure and does not use any memories such as SRAM,so the area of the core is very small.The core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The core is available optimized for several technologies with competitive utilization and performance characteristics.
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应用：
特色：
FIPS 46-3 Standard Compliant
Simple interface and timing
Fully Synchronous design.
Iterative structure
Small gate count
Encoding and decoding operations are performed in 17 clocks (ECB mode)
DES01_eSolutions.rar
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