类型：软IP
简短描述：ES3DES02是一种采用流水线结构，用可综合的Verilog HDL语言风格进行设计的实现Triple Data Encryption Standard (3DES)加解密算法标准的IP软核。
详细描述：
The ES3DES02 core is the Verilog HDL synthesizable model to implement the Triple Data Encryption Standard (3DES) documented in the U.S. Government publication FIPS 46-3.The core is a block cipher, working on 64 bits of data at a time. It is built upon the Data Encryption Standard (DES) core. The core uses 192 bits key of which only 168 bits are used. The design uses the pipeline structure and does not use any memories such as SRAM,so the data processing speed is very high. After an initial latency of 56 cycles, it can output encryption/decryption at every cycle. The core is fully synchronous using only one clock signal and can be implemented in both FPGAs and ASICs. The core is available optimized for several technologies with competitive utilization and performance characteristics.
工艺：
代工厂：
应用：
特色：
Simple interface and timing
Fully Synchronous design.
Pipeline structure
High performance,high data throughput
Encryption/Decryption performed in 1 cycle (ECB mode) after an initial latency of 56 cycles
3DES02_eSolutions.rar
您当前的位置：
