The AU-NB9003 Utopia 1/2/2+/3/3+ AMBA Subsystem provides a Utopia 1/2/2+/3/3+
peripheral subsystem for AMBA based SOCs. It contains a Utopia 1/2/2+/3/3+ Interface between
UTOPIA/POS-PHY compliant PHY Chips and the application layers such as ATM. This Utopia
Interface connects seamlessly to the AMBA AHB Bus. A DMA Engine is included to move the
packet/cell data. The figure below shows the Utopia 1/2/2+/3/3+ Subsystem used within an SOC.
The Utopia 1/2/2+/3/3+ AMBA Subsystem Core is available as a synthesizable Verilog model
from Aurora VLSI, Inc.

Utopia 1/2/2+/3/3+
• Supports both ATM Forum’s standards and Saturn Group’s POS-PHY Interface
standards.
• Programmable option for U1, U2, U2+(or POS-PHY Level 2), U3, and U3+
standards.
• Supports both packet and cell level transfers.
• Number of ports for polling can be programmed.
• Receive Ports can be enabled or disabled dynamically.
• Transfer (PHY/core transfer length for every transfer) count can be independently
programmed for each port with a maximum of 64 bytes.
• Round robin mechanism of polling on the receive side.
• Parity generation/checking with a programmable polarity option.
• User defined (through Verilog parameters) FIFO sizes for all transmit and receive
FIFOs.
• Supports synchronous memories for FIFOs.
• Synthesis options for receive only, transmit only, or both receive and transmit.
DMA/Host Interface
• AMBA AHB Bus interface
• 2 channel DMA Engine
- transmit data DMA from data source to Transmit Data FIFO
- receive data DMA from Receive Data FIFO to data destination
• Physical DMA addresses
• Programmable DMA starting address
• Programmable DMA transfer count- up to 64 Kbytes
• Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
• Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
• Locked DMA operation optional (software programmable)
• Direct software writes or information extracted from descriptors in memory, to
program DMA control information
• Dedicated AMBA Bus master interface for each DMA channel
• AMBA Bus slave interface for
- register reads and writes
- writes to the Transmit Address FIFO
- reads of the Transmit Status FIFO