This core is an interface between UTOPIA/POS-PHY compliant PHY Chips and the application
layers such as ATM. It operates in full duplex mode with PHY devices and supports up to 31
devices with a maximum data rate of 3.2 Gb/s. It is compliant to UTOPIA Level 3, Level 2, Level
1 Standards and POS-PHY Level 2 and 3 standards. Its mode can be switched between U1, U2
and U3. It is the Utopia master. The Utopia Core is available as a synthesizable Verilog model
from Aurora VLSI, Inc.

• Supports both ATM Forum’s standards and Saturn Group’s POS-PHY Interface
standards.
• Programmable option for U1, U2, U2+(or POS-PHY Level 2), U3, and U3+
standards.
• Supports both packet and cell level transfers.
• Number of ports for polling can be programmed.
• Receive Ports can be enabled or disabled dynamically.
• Transfer (PHY to core transfer length for every transfer) count can be independently
programmed for each port with a maximum of 64 bytes.
• Round robin mechanism of polling on the receive side.
• Parity generation/checking with a programmable polarity option.
• User defined (through Verilog parameters) FIFO sizes for all transmit and receive
FIFOs.
• Compatible receive and transmit application interfaces to design loop back at Utopia
master level.
• Supports synchronous memories for FIFOs.
• Synthesis options for receive only, transmit only, or both receive and transmit.
• Simple configuration register interface to application logic.