类型：软IP
简短描述：USB 2.0 Device Core
详细描述：
The SSU7320 USB 2.0 Device Core provides USB 2.0 Device functionality. It includes the
required endpoints plus eight bulk/iso transfer endpoints. This USB 2.0 Device Core is available
as a synthesizable Verilog model from Aurora VLSI, Inc.
工艺：
代工厂：
应用：
特色：
• Ten endpoints:
- EP0- control endpoint, accepts SETUP, IN, and OUT control transactions
- EP1- interrupt endpoint, accepts IN and OUT interrupt transactions
- EP2, EP4, EP6, EP8- IN endpoints; accept IN bulk and isochronous
transactions
- EP3, EP5, EP7, EP9- OUT endpoints; accept OUT bulk and isochronous
transactions
• 8 or 16 bit UTMI interface
• Accepts stalls from the application logic
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