类型：软IP
简短描述：USB 1.1 Device Core (Mini Version)
详细描述：
The SSU7211 USB 1.1 Device Core provides USB 1.1 Device functionality. It minimizes gate
count by including only the required endpoints plus two bulk/iso transfer endpoints. This USB
1.1 Device Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.
工艺：
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应用：
特色：
• Four endpoints:
- EP0- control endpoint, accepts SETUP, IN, and OUT control transactions
- EP1- interrupt endpoint, accepts IN and OUT interrupt transactions
- EP2- IN endpoint; accepts IN bulk and isochronous transactions
- EP3- OUT endpoint; accepts OUT bulk and isochronous transactions
• Serial interface to PHY transceiver chip
• Accepts stalls from the application logic
• Low gate count
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