The AU-F8081 IEEE 1394b + OHCI Core provides an IEEE 1394b Link Layer Controller that
supports the industry standard Open Host Controller Interface (OHCI) version 1.2. OHCI is
included to provide DMA packet data transfers, interrupts, and other OHCI compatible features.
The figure below shows IEEE 1394b + OHCI Core usage within an SOC. The IEEE 1394b +
OHCI Core is available as a synthesizable Verilog model from Aurora VLSI, Inc.

IEEE 1394b Link Layer Controller
• Compliant with IEEE 1394b
• IEEE 1394b link layer functionality
• IEEE 1394b-2002 parallel PHY interface
• Supports 100, 200, 400, 800, and 1600 mbits/s
• Cycle master capability
• Generates CRC for transmit and checks CRC for receive packets
• Asynchronous and isochronous transfers are supported
• Packet status captured
• PHY status and cycle sync status
Open Host Controller Interface
• Compliant with OHCI 1.2
• 4 channel DMA Engine
- asynchronous transmit data DMA from data source to Async Transmit FIFO
- isochronous transmit data DMA from data source to Iso Transmit FIFO
- asynchronous receive data DMA from Receive FIFO to data destination
- isochronous receive data DMA from Receive FIFO to data destination
• Up to 32 isochronous transmit DMA contexts- user configurable
• Up to 32 isochronous receive DMA contexts- user configurable
• Asynchronous transmit data FIFO- 16 bytes to 32K bytes user configurable
• Isochronous transmit data FIFO- 16 bytes to 32K bytes user configurable
• Asynchronous receive data FIFO- 16 bytes to 32K bytes user configurable
• Isochronous receive data FIFO- 16 bytes to 32K bytes user configurable
• All OHCI 1.2 configuration, control, and status registers
• All OHCI 1.2 interrupts