The AU-FB8011 IEEE 1394a + OHCI AMBA Subsystem provides an IEEE 1394a peripheral
subsystem for AMBA based SOCs. It contains an IEEE 1394a Link Layer Controller that
connects seamlessly to the AMBA AHB Bus. The Open Host Controller Interface (OHCI) is
included to provide DMA packet data transfers, interrupts, and other OHCI compatible features.
The figure below shows IEEE 1394a + OHCI Subsystem usage within an SOC. The IEEE 1394a
+ OHCI AMBA Subsystem Core is available as a synthesizable Verilog model from Aurora
VLSI, Inc.

IEEE 1394a Link Layer Controller
• Compliant with IEEE 1394a
• IEEE 1394a link layer functionality
• IEEE 1394a-2000 PHY interface and IEEE 1394-1995 Annex J.PHY interface
• Supports 100, 200, and 400 mbits/s
• Cycle master capability
• Generates CRC for transmit and checks CRC for receive packets
• Asynchronous and isochronous transfers are supported
• Packet status captured
• PHY status and cycle sync status
OHCI/AMBA Interface
• Compliant with OHCI 1.2
• AMBA AHB Bus interface
• 4 channel DMA Engine
- asynchronous transmit data DMA from data source to Async Transmit FIFO
- isochronous transmit data DMA from data source to Iso Transmit FIFO
- asynchronous receive data DMA from Receive FIFO to data destination
- isochronous receive data DMA from Receive FIFO to data destination
• Up to 32 isochronous transmit DMA contexts- user configurable
• Up to 32 isochronous receive DMA contexts- user configurable
• Asynchronous transmit data FIFO- 16 bytes to 32K bytes user configurable
• Isochronous transmit data FIFO- 16 bytes to 32K bytes user configurable
• Asynchronous receive data FIFO- 16 bytes to 32K bytes user configurable
• Isochronous receive data FIFO- 16 bytes to 32K bytes user configurable
• All OHCI 1.2 configuration, control, and status registers
• All OHCI 1.2 interrupts
• 2 AMBA Bus masters
- asynchronous and isochronous transmit DMA
- asynchronous and isochronous receive DMA
• AMBA Bus slave for configuration, control, and status register accesses