The AU-FB8010 IEEE 1394a AMBA Subsystem provides an IEEE 1394a peripheral subsystem
for AMBA based SOCs. It contains an IEEE 1394a Link Layer Controller that connects
seamlessly to the AMBA AHB Bus. A DMA Engine is included to move packet data. The figure
below shows its use within an SOC. The IEEE 1394a AMBA Subsystem Core is available as a
synthesizable Verilog model from Aurora VLSI, Inc.

IEEE 1394a Link Layer Controller
• Compliant with IEEE 1394a
• IEEE 1394a link layer functionality
• IEEE 1394a-2000 PHY interface and IEEE 1394-1995 Annex J.PHY interface
• Supports 100, 200, and 400 mbits/s
• Cycle master capability
• Generates CRC for transmit and checks CRC for receive packets
• Asynchronous and isochronous transfers are supported
• Separate transmit data FIFOs for asynchronous and isochronous packets
• Receive data FIFO for incoming packets
• Packet status captured in 2 status FIFOs
- Transmit Status FIFO- 4 entries
- Receive Status FIFO- 4 entries
• PHY status and cycle sync status are provided
DMA/AMBA Interface
• AMBA AHB Bus interface
• 3 channel DMA Engine
- asynchronous transmit data DMA from data source to Async Transmit FIFO
- isochronous transmit data DMA from data source to Iso Transmit FIFO
- receive data DMA from Receive FIFO to data destination
• Physical DMA addresses
• Programmable DMA starting address
• Programmable DMA transfer count- up to 64 Kbytes
• Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
• Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
• Locked DMA operation optional (software programmable)
• Direct software writes or information extracted from descriptors in memory, to
program DMA control information
• Dedicated AMBA Bus master interface for each DMA channel
• AMBA Bus slave interface for register reads and writes- configuration, control, and
status
• Interrupts:
- transmit packet DMA completed
- receive packet DMA completed
- packet transmit completed
- packet receive completed