The AU-PB8064 64 Bit PCI AMBA Subsystem provides a 64 Bit PCI peripheral subsystem for
AMBA based SOCs. It contains a 64 Bit PCI Bus Interface with PCI master and slave
functionality. The 64 bit PCI AMBA Subsystem connects seamlessly to the AMBA AHB Bus.
A DMA Engine is included to move data of PCI master memory and I/O transactions. PCI
master configuration transaction data is transferred by direct AMBA Bus reads and writes. PCI
slave transactions are translated into AMBA Bus transactions by the 64 Bit PCI AMBA
Subsystem and driven onto the AMBA Bus. The figure below shows the 64 Bit PCI AMBA
Subsystem within an SOC. The 64 Bit PCI AMBA Subsystem Core is available as a
synthesizable Verilog model from Aurora VLSI, Inc.

64 Bit PCI Bus Interface
• PCI 2.1 and 2.2 compliant
• Master and slave support 64 bit address and data transfers
• Supports variable burst size transfers
• Performs zero wait state transfers
• Master is capable of performing I/O, Memory, and Configuration types of PCI
transfers
• Master supports byte mode operation
• Master is capable of performing Memory Write Invalidate and Memory Read Line
operations
• Performs back to back transfers
• PCI master transaction status captured in eight entry PCI Master Status FIFO
DMA/AMBA Interface
• AMBA AHB Bus interface
• Single channel DMA Engine for PCI master memory and I/O transactions
• Physical DMA addresses
• Programmable DMA starting address
• Programmable DMA transfer count- up to 64 Kbytes
• Programmable DMA AMBA Bus interface transaction size- 8 to 1024 bytes
• Programmable DMA AMBA Bus data transfer size- 4 or 8 bytes
• Locked DMA operation optional (software programmable)
• Direct software writes or information extracted from descriptors in memory, to
program DMA control information
• Dedicated AMBA Bus master interface for the DMA channel
• Dedicated AMBA Bus master interface for PCI slave transactions
• Unique PCI slave address to AMBA Bus address mapping for each PCI slave address
space
• AMBA Bus slave interface for register reads and writes and PCI master configuration
transactions
• Interrupts:
- PCI master write data to PCI Bus Interface DMA completed
- PCI master read data from PCI Bus Interface DMA completed
- PCI master transaction status available
- PCI Bus interrupt