The AU-G0600 Serial Peripheral Interface (SPI) AMBA APB Core provides an industry standard
Serial Peripheral Interface (SPI) for AMBA based SOCs. It supports master (including multi
master) and slave SPI modes with SPI word lengths up to 32 bits. Either the most significant bit
or least significant bit of each SPI word may be transferred first. All four combinations of SPI
clock idle polarity and SPI clock data transfer phase are implemented. The SPI AMBA APB
Core connects seamlessly to the AMBA APB Bus as an AMBA Bus slave. The Serial Peripheral
Interface (SPI) AMBA APB Core is available as a synthesizable Verilog model from Aurora
VLSI, Inc.

• Master mode including multi master capability, and slave mode
• Transmit and receive SPI word lengths up to 32 bits- software configurable
• MSB or LSB transferred first- software configurable
• Implements all SPI clock polarity and clock phase modes
• Master mode:
- supports 16 SPI slaves
- configurable SPI clock period- resolution of 2 x AMBA clock period
- software configurable delay to first clock of each SPI word
- optional wait signal to delay first clock of each SPI word
- optional de-assertion of slave selects between each SPI word
- hardware generated or software driven slave selects- configurable
- SPI clock, slave select, and data outputs support push pull (both driven and
hiZ when de-asserted), and open drain pad drivers
- optionally detects master collision error with multiple masters
• Slave mode:
- sign or zero extend receive data to fill AMBA bus datum
- last data or zero sent on transmit underrun
- drop or overwrite on receive overrun
- optional wait/enable output
- master broadcast supported
- data and wait outputs support push pull (both driven and hiZ when deasserted),
and open drain pad drivers
• AMBA interface
- byte, halfword, or word AMBA bus datum size- configurable
- one SPI word per AMBA bus datum of the same or greater size
- Each 32 bit AMBA bus transfer is packed with four AMBA data bytes, two