The AU-G0500 General Purpose I/Os (GPIOs) AMBA APB Core provides a GPIO peripheral for
AMBA based SOCs. It contains 32 General Purpose I/Os (GPIOs) that connect seamlessly to the
AMBA APB Bus as an AMBA Bus slave. The General Purpose I/Os AMBA APB Core is
available as a synthesizable Verilog model from Aurora VLSI, Inc.

• 32 GPIOS
• Register or bypass mode selected independently for each GPIO
• Independent direction control for each GPIO
• Output data can be
- programmed, set, or cleared over the AMBA bus (register mode)
- driven directly to the output pins (bypass mode)
• Output enable can be
- programmed over the AMBA bus (register mode)
- driven directly to the output pins (bypass mode)
• Output enable assertion polarity is user configurable
• Input data can be
- captured and read over the AMBA bus (register mode)
- directly available from the input pins (bypass mode)
• Independent interrupt enable for each GPIO
• GPIO inputs are deglitched for interrupt detection
• Level or edged sensitive interrupts- independently configured for each interrupt
• High or low interrupt polarity- independently configured for each interrupt